CD Ware Multimedia 1994 November/Cd Ware (Nro. 2) - Epimundo.iso/DOS/ED/PCKEY.ZIP/EXSIZE5.SCR

Text File | 1993-05-25 | 20.5 KB | 1,137 lines

:exsize5.scr

if memory 1 ! 12 goto exit
if memory 2 > 0 goto lesson2
goto start_lesson

:repeat_lesson
bkey r
bkey '

:start_lesson
clear 15

cursor 22 19
print 'Press any key to start lesson 14.
wait -
clear 19 19

clear 15
cursor 2 16
print 'Here is the final - for now at least - example draft of text. It contains
cursor 0 17
print 'plenty of numbers etc. Remember, try not to correct any mistakes you make but
cursor 0 18
print 'carry on with the rest of the text. It is easier to correct errors when you have
cursor 0 19
print 'finished typing.

pass 90
if auto ! 0 auto
script - stspeed

script - waitspc
start 2

:again
start 3

clear 15
cursor 9 16
print 'The 80486 comprises more than a million transistors, linked
cursor 9 20
print 'together to form on-chip functional equivalents for three
cursor 9 16
test -
scroll 4 15 22
cursor 9 20
print 'previously descrete chips: the 80386, including its
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'demand-paged and virtual memory management, 4Gbyte direct
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'addressing range, and 64 terabytes of virtual memory
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'space; the 80387 with a binary-compatible 80-bit IEEE 754
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'floating-point unit running in parallel with the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print '80386-compatible 'integer unit'; and the 82385 cache
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'controller, with 8k of mixed data and instruction cache
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'memory.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'In other words, add some main memory and some input and
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'output hardware, and the 80486 on its own can form the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'heart of a system with all the features of today's top
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print '80386-based PCs. Such a system would also be faster than
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'an 80386-based machine running at the same clock rate, for
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'no other reason than that the RAM cache and its controller
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'are on the processor chip instead of separated from it by
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'a comparatively enormous expanse of sluggish copper
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'connector.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'But instead of just bolting these functional blocks
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'together on a chip and leaving it at that - and despite
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'having to maintain compatibility with the 8086 processor
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'design that is now ten years old - intel's engineers have
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'improved the efficiency of the processor instruction set,
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'speeded up the cache architecture, and added other
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'performance enhancements.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'For example, the 80486 instruction set has been designed
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'to execute frequently used instructions in a single clock
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'cycle as much as possible by loading five instructions
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'into a pipe-line and executing parts of them in parallel.
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'This means that a LOAD instruction that would take four
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'cycles on an 80386 and two cycles on the Sun SPARC reduced
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'instruction set computing (RISC) processor, takes one
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'cycle on an 80486. Similarly, a CALL instruction that
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'takes three cycles on the new chip compares with nine on
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'the 80386 and three on the SPARC.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'Other internal shortcuts remove the wait-state that is
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'normally required before data read from cache is available
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'for processing; another allows the results of previous
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'instructions to be available to subsequent ones faster
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'than normal. And in the 80387-compatible floating-point
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'unit, 80387 instructions similarly take fewer clock cycles
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'to execute; for instance, an 80-bit floating-point store
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'takes three cycles rather than the fifteen or twenty of
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'the external 80387.
enter
cursor 9 16
test -

cursor 9 20
test -

script - sofar
if accuracy 3 < 90 goto again
if key = R goto repeat_lesson
if key = r goto repeat_lesson

memory 2 = 1
goto start_lesson2

:lesson2
if memory 2 > 1 goto lesson3
goto start_lesson2

:repeat_lesson2
bkey r
bkey '

:start_lesson2
clear 15
cursor 26 18
print 'Now for part 2 of lesson 14.

pass 90
if auto ! 0 auto
script - stspeed

script - waitspc
start 2

:again2
start 3

clear 15
cursor 9 16
print 'The cache architecture in the chip is now what is called
cursor 9 20
print ''four-way set-associative cacheing of the external 82385
cursor 9 16
test -
scroll 4 15 22
cursor 9 20
print 'controller. To see why this is better, consider the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'problem of finding out whether a particular item of data
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'is in the local cache RAM or still in main RAM in an ideal
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'world, the cache RAM would simply hold the contents of the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'last 'n' memory locations accessed by the main processor,
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'where 'n' is the number of locations whose contents just
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'fill the cache space This sort of ideal cache is 'fully
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'associative', since any cache location can hold the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'contents of - or be 'associated' with - any location in
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'main memory, but it is also inefficient because every
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'location in the cache must be checked by the cache
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'controller to see if the location required is there, As
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'cache size grows, the overhead involved in doing fully
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'associative cacheing becomes prohibitive.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'So what is required is a means of reducing the area that
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'the cache controller has to check for a particular
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'location to log a cache hit or a miss, and this is done by
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'mapping the cache onto main memory in sets. To see how
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'this works, say the processor ask for location 38000 out
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'of a total number of 64000 locations. Now, the cache
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'controller has to find out whether the contents of that
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'location are in the cache, and so goes through the flags
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'set by each cache entry to signal the main RAM locations
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'whose contents they hold. With a fully-associative cache,
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'the controller has to check every flag value. With a
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'two-way set-associative cache, the controller knows that
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'locations above 32000 can only go in the set made up by
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'the top half of the cache, and so only has to check half
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'as many flags. With a four-way set-associative cache, the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'controller knows that if location 38000 is in the cache at
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'all, it is in that quarter of it that is mapped onto
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'locations between 32000 and 48000, again reducing the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'controller's area of search.
enter
cursor 9 16
test -

cursor 9 20
test -

script - sofar
if accuracy 3 < 90 goto again2
if key = R goto repeat_lesson2
if key = r goto repeat_lesson2

memory 2 = 2
goto start_lesson3

:lesson3
if memory 2 > 2 goto lesson4
goto start_lesson3

:repeat_lesson3
bkey r
bkey '

:start_lesson3
clear 15
cursor 26 18
print 'Now for part 3 of lesson 14.

pass 90
if auto ! 0 auto
script - stspeed

script - waitspc
start 2

:again3
start 3

clear 15
cursor 9 16
print 'There needs to be some kind of compromise between the
cursor 9 20
print 'number of sets a set-associative cache is divided into and
cursor 9 16
test -
scroll 4 15 22
cursor 9 20
print 'the search time for a hit or miss; the more set divisions
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'there are the faster the controller's search but, the more
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'divisions there are, the more logic and processing is
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'involved in assigning each main RAM read to the right set.
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'And when the cache has to decide on a hit or miss in
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'around 10ns if RAM cacheing is to be effective at all, a
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'four-way set-associative cache inside the processor chip
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'is superior to a two way set-associative cache using
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'external controller and RAM. More, although the 80486
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'cache is write-through so that writes to cache are
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'immediately written to main RAM as well, write buffering
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'is used so that the processor can continue processing
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'after posting a cache write to the buffer without having
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'to wait for any delays in writing through to main RAM. And
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'there is also 'bus snooping', as with the 82385, to make
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'sure that direct memory access (DMA) transfers do not
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'cause main RAM and cache RAM to get out of step.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'On the other hand, a cache is no good unless main RAM is
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'fast enough to keep it filled. The 80486 data bus has a
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'new mode that reacts to a cache miss by 'burst-filling'
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'the cache and instruction pre-fetch queue at the rate of a
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print '64-bit double word per clock cycle, meaning that if a
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'cache miss occurs the cache is filled up with other
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'possibilities as fast as possible. With this 'burst bus
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'transfer' mechanism, up to 80Mbytes of data per second can
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'be read on the data bus at a clock speed of 25MHz.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'The bus-snooping features are combined with new
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'instructions that match the system of semaphores and
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'signals used by OS/2 and Unix to let programs flag their
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'alterations to shared memory resources, in a
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'multi-tasking, multi-user or multi-processor environment.
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'Intel is working with AT&T, Unisys subsidiary and major
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'Unix OEM supplier Convergent Technologies, Olivetti and
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'Prime to create a multi-proccessor version of Unix System V
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'Release 4 for the 80486, the 80386 and the i860, scheduled
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'for release before the end of this year.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'In all this, the one thing to remember is that none of it
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'matters as far as software is concerned. The instruction
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'set of the 80486 is completely compatible with every
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'instruction currently aimed at the 80386 and 80387, and
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'everything that runs on an 30386 will run, barring
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'disaster, on the 80486 as well. The 80486 also has the big
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'advantage that since it includes the 80387 circuitry, any
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'program aimed specifically at the 80486 can assume that
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'fast floating-point functions are available. As Apple
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'found with the Macintosh II and every new Macintosh since,
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'building a maths co-processor into every machine means
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'that programmers actually get around to using it instead
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'of aiming at the co-processor less lowest common
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'denominator.
enter
cursor 9 16
test -

cursor 9 20
test -

script - sofar
if accuracy 3 < 90 goto again3
if key = R goto repeat_lesson3
if key = r goto repeat_lesson3

memory 2 = 3
goto start_lesson4

:lesson4
if memory 2 > 3 goto exit
goto start_lesson4

:repeat_lesson4
bkey r
bkey '

:start_lesson4
clear 15
cursor 22 18
print 'And now for the rest of the article.

pass 90
if auto ! 0 auto
script - stspeed

script - waitspc
start 2

:again4
start 3

clear 15
cursor 9 16
print 'So, the 80486 is more highly integrated and better
cursor 9 20
print 'designed than the 80386, so that it runs 80386 programs
cursor 9 16
test -
scroll 4 15 22
cursor 9 20
print 'faster at 25MHz than an 80386 can manage at 33MHz. Is that
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'enough to kill the 80386 in favour of the new chip?
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'Well, no it isn't, but then that is not the full story.
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'The 80386 is an old chip in the accelerated timescales of
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'the electronics industry, since the first samples shipped
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'to IBM, Compaq, and - presumably in line for cast-offs,
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'ALR - in the autumn of 1985. At that time the chip came in
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print '12MHz and 16MHz versions, and that implies that the
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'designed-in speed was 16MHz, while the 12MHz parts were
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print '16MHz chips that did not quite make the final tests. So
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'what is the 80386 doing running at 33MHz, twice its
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'original design speed? Using scaling techniques to reduce
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'chip size and electronic signal path length, taking care
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'of quality control during manufacture, and adding some
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'tweaks in the design to cope with interference at higher
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'frequencies, a 16MHz processor can be converted into a
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'low-volume 33 MHz processor with associated high prices
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'due to low production volumes.
enter
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'But doubling the clock speed of a processor design using
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'standard manufacturing techniques is pushing things, and
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'going beyond 40MHz as an absolute maximum is going too
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'far. However, the 80486 arrives at a clock speed of 25MHz
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'with 33MHz to come, implying that the initial chip design
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'is meant to run at a minimum 33MHz. There is more speed to
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'come, maybe a factor of two more, as the chip passes
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'through the normal processor development cycle. The launch
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'of the Motorola 68030 processor running at 50MHz, compared
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'with the maximum 25MHz of the older but
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'software-compatible 68020, shows precisely what will
cursor 9 16
test -

scroll 4 15 22
cursor 9 20
print 'happen with the 80486 compared with the 80386.
enter
cursor 9 16
test -

cursor 9 20
test -

script - sofar
if accuracy 3 < 90 goto again4
if key = R goto repeat_lesson4
if key = r goto repeat_lesson4

memory 2 = 0

memory 1 = 7

clear
cursor 51 7
print '14
script save

:exit